1. Field of the Invention
The present invention relates to an active matrix circuit fabricated using thin film insulated gate type semiconductor devices (thin film transistors or TFTs) formed on an insulating substrate (in this specification, the xe2x80x9cinsulating substratexe2x80x9d generally means a material having an insulating surface and, unless otherwise defined, it implies not only an insulating material such as glass but also a material such as a semiconductor or metal having an insulator layer formed thereon). More particularly, the present invention relates to a monolithic active matrix circuit which includes peripheral circuits for driving it formed on the same substrate. A monolithic active matrix circuit according to the present invention is suitable for matrix type displays such as liquid crystal displays and plasma displays.
2. Description of the Related Art
As shown in FIG. 5, a monolithic active matrix circuit is comprised of an active matrix circuit area, a source driver, and a gate driver which are formed using substantially the same process. In an active matrix circuit, TFTs are used as switching elements for liquid crystal cells. In order to supplement the electrostatic capacity of the liquid crystal cells, auxiliary capacities are provided in parallel with the liquid crystal cells. The peripheral circuits such as the source driver and gate driver are constituted by a shift register and switching elements which must be capable of operating at high speed. Taking this into consideration, monolithic active matrix circuits are constructed using a crystalline semiconductor (e.g., polycrystalline silicon). Further, in order to suppress power consumption, the peripheral circuits are constructed using complementary circuits (CMOS). Such techniques are described in Japanese unexamined patent publication (KOKAI) No. H1-289917 in which switching TFTs in an active matrix circuit and a TFT that constitutes a shift register of a peripheral circuit are described as having substantially the same sectional structure.
However, TFTs as the switching elements in an active matrix circuit and TFTs in CMOS circuits such as a shift register do not operate in the same way. For example, for a TFT as a switching element, a high reverse bias voltage (a negative voltage if the TFT is of the N-channel type) is applied to the gate electrode. On the other hand, principally, no reverse bias voltage is applied to a TFT in a CMOS logic circuit. Further, the operating speed of the former may be one percent or less of the speed required for the latter.
As described above, it has been considered undesirable to employ the same structure to build TFTs for which operating conditions and required characteristics are greatly different.
It is an object of the present invention to optimize an active matrix circuit and peripheral circuits thereof by differentiating the structure of TFTs as the switching elements used in the active matrix circuit from that of TFTs used for CMOS logic circuits such as shift registers of the peripheral circuits.
Specifically, the source and drain of a TFT of an active matrix circuit are substantially doped with only one of two types of impurities, i.e., N-type and P-type impurities, whereas the source and drain of a TFT of a peripheral circuit which is of the same conductivity type as the TFT of the active matrix circuit are doped with both of N-type and P-type impurities.
If a TFT of the active matrix circuit is of the P-channel type, the source and drain thereof are doped with only P-type impurities. On the other hand, the source and drain of a P-channel type TFT of a peripheral circuit are doped with both of P-type and N-type impurities. Needless to say, in general, the density of P-type impurities is higher than that of N-type impurities.
The present invention is characterized in that the structure of a TFT is optimized using side walls formed on both sides of the gate electrode and a gate line thereof.
The side walls according to the present invention are formed by coating the gate electrode and gate line with an insulator film and by etching the film on an anisotropic basis. The substantially triangular insulators (side walls) formed on both sides of the gate electrode and gate line are used as masks during doping to form a low density drain (lightly doped drain, LDD) structure, an offset gate structure, and the like.
A process of providing an LDD through the formation of such side walls will be described with reference to FIG. 1. First, a crystalline semiconductor region 103 in the form of an island is formed on a substrate 101. An insulated base film 102 may be formed on the substrate. After depositing a gate insulation film 104, a gate electrode 105 and a gate line 106 are formed using appropriate materials. As the materials for the gate electrode and gate line, materials which can be anodized, e.g., aluminum, may be used. (See FIG. 1A)
Thereafter, the semiconductor region is irradiated by accelerated ions of the doping impurities to form an impurity region 109 with the gate electrode 105 serving as a mask. If phosphorous is used as the doping impurities, an N-type impurity region is obtained and, if boron is used, a P-type impurity region is obtained. The conductivity of the impurities can be controlled by adjusting the densities and mixing ratio of those impurities. The amount of doping (dose) must be kept small in order to obtain an LDD structure. If no doping is performed, an offset gate structure is obtained. High density doping will provide normal source and drain. (See FIG. 1B)
The gate electrode and gate line may be anodized before doping to form an anodic oxide film 108. This anodic oxide film will serve as an etching stopper to protect the gate electrode during an anisotropic etching process to be performed later. The same effect can be obtained by forming a coating film such as a silicon nitride film on the gate electrode.
Thereafter, an insulator film 110 is formed to cover the gate electrode and gate line (and the anodic oxide film surrounding them). This film must be formed with sufficient coating properties and preferably has a thickness in the range of one-third to twice the height of the gate electrode and the gate line. For such a purpose, it is preferable to use a chemical vapor deposition (CVD) process such as a plasma CVD process, a low-pressure CVD process, and an atmospheric pressure CVD process. As a result, the thickness of the silicon nitride film is increased at the sides of the gate electrode and gate line as indicated by the dotted lines shown FIG. 1C.
The insulator formed as described above is subjected to anisotropic etching which proceeds with priority to etching in a direction substantially perpendicular to the substrate. This etching must be performed until the insulator film 110 is etched at flat portions and may be continued until the underlying gate insulation film is etched. This leaves substantially triangular insulators (side walls) 111 and 112 at the sides of the gate electrode and gate line because the insulator film has been made thicker in those areas than other areas. (See FIG. 1D)
Then, high density impurity doping is carried out using the side walls 111 and 112 as doping masks to form source and drain 114. LDD regions 113 are formed in the areas under the side walls because doping is not performed in those areas. (See FIG. 1E)
Thereafter, the impurities which have been doped are activated by means of thermal annealing, irradiation with intense light such as laser light or equivalents thereof (optical annealing) or the like. Further, after a layer insulator 115 is formed, a contact hole is formed in one or both of the source and drain of the TFT to form lines 116 and 117 for a second layer. (See FIG. 1F)
The above-described steps provide a TFT having an LDD structure. Although not true only for an LDD structure, the structure shown in FIG. 1 wherein the side walls 112 are provided on the sides of the gate line 106 is found to be effective for preventing the second layer wiring 117 from being cut at the steps it forms where it extends over the gate line 106 because the side walls 112 reduce the steepness of the steps.
An LDD structure and an offset gate structure can be provided as described above. According to the present invention, an LDD structure is employed for an N-channel type TFT for which a counter measure against hot carriers must be taken, whereas a normal structure or an offset gate structure is employed for a P-channel type TFT for which such a counter measure is not required. According to the present invention, a TFT used for an active matrix circuit may be of either the N-channel type or P-channel type. However, a P-channel type TFT is preferred because it suffers less deterioration in characteristics. The present invention will be described below with reference to preferred embodiments thereof.